Samsung LNB50 Uživatelský manuál stáhnout pdf (Strana 42)

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The system clock can also be derived from an external oscillator by doing one of

the following:

• Driving an external oscillator from Y5 into X1 and using the internal PLL (see

location H16 in Figure 2-2 on page 2-3)

• Driving an external oscillator from Y5 into X1 and bypassing the internal PLL

The PLL can be configured in 1x, 2x (default), or 4x PLL mode or PLL bypass

mode by appropriately setting the pinstraps on SW16. See “Debug and

Configuration Circuitry” on page 2-39 for more information.

The maximum crystal input and oscillator frequencies are 40 MHz. The CDP

provides pin sockets, allowing the designer to easily attain multiple clock

configurations.

NOTE: When using an external oscillator or clock source to drive the system, USB,

or UART clock, you must drive the clock with a source that does not exceed the

Am186CC/CH/CU microcontroller’s V

Figure 2-6. Am186™CC/CH/CU Microcontroller System Clock

Ecliptek EC2-24.000M-CL150

Ecliptek EC1300HS-XX

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Samsung LNB50 Uživatelský manuál Strana 42