
PRODUCT INFORMATIONPRODUCT INFORMATION
6.4 VDD Power Dip Sequence
T
d
V
CC
V
DD
90%
80%
GND
4.5V ≤ V
DD
≤ 5.5V
If V
DD
(typ.) x 80% ≤ V
CC
≤ V
DD
(typ) x 90%,
then 0<Td ≤20msec
Note (1) The above conditions are for the glitch of the input voltage.
(2) For stable operation of an LCD Module power, please follow them.
i.e., if typ VDD x 80% ≤ Vcc ≤ typ VDD x 90%, then T
d
should be less than 20ms.
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