
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 1 of 19DDR2 Unbuffered SDRAM MODULE240pin Unbuffered Module based on 2Gb A-die64/72-bit Non-ECC/ECC68FBGA with Lead-
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 10 of 19 Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under al
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 11 of 19 Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level app
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 12 of 19(IDD values are for full operating range of Voltage and Temperature)Symbol Proposed Conditions Units NoteIDD
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 13 of 1912.1 M378T5263AZ(H)3 : 4GB(256Mx8 *16) Module12.2 M391T5263AZ(H)3 : 4GB(256Mx8 *18) ECC Module(TA=0oC, VDD=
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 14 of 19(VDD=1.8V, VDDQ=1.8V, TA=25oC)Note : DM is internally loaded to match DQ and DQS identically.ParameterSymbol
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 15 of 19(Refer to notes for informations related to this table at the component datasheet)Parameter SymbolDDR2-800 D
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 16 of 19Parameter SymbolDDR2-800 DDR2-667UnitsNotesmin max min maxFour Activate Window for 1KB page size products tF
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 17 of 19(Refer to notes for informations related to this table at the component datasheet)Parameter SymbolDDR2-533Un
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 18 of 19Parameter SymbolDDR2-533Units Notesmin maxFour Activate Window for 1KB page size products tFAW 37.5 x nsFour
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 19 of 19Units : MillimetersThe used device is 256M x8 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T2G084QA256Mbx8 based
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 2 of 19Table of Contents1.0 DDR2 Unbuffered DIMM Ordering Information ...
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 3 of 19Revision HistoryRevision Month Year History1.0 December 2007 - Initial Release1.1 July 2008 - Applied JED
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 4 of 191.0 DDR2 Unbuffered DIMM Ordering Information2.0 FeaturesNote : 1. “Z” of Part number(12th digit) stands for
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 5 of 19NC = No Connect, RFU = Reserved for Future Use1. The TEST pin is reserved for bus analysis tools and is not c
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 6 of 19NC = No Connect, RFU = Reserved for Future Use1. The TEST pin is reserved for bus analysis tools and is not c
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 7 of 19Symbol Type DescriptionCK0-CK2CK0-CK2InputCK and CK are differential clock inputs. All the SDRAM addr/cntl in
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 8 of 19(Populated as 2 rank of x8 DDR2 SDRAMs)8.1 4GB, 512Mx64 Module - M378T5263AZ(H)38.0 Functional Block Diagram
Rev. 1.1 July 2008UDIMMDDR2 SDRAM 9 of 19(Populated as 2 rank of x8 DDR2 SDRAMs)8.2 4GB, 512Mx72 ECC Module - M391T5263AZ(H)3S0DQS0DQS0DM0DM CS DQS DQ
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